The present invention relates to a method of controlling the transfer of read data, having a data length corresponding to a data bus width, between a high-speed input/output device (e.g., a magnetic disk drive) and a main memory for interleaving data having a data length which is a plurality of times the data bus width, and an input/output channel apparatus for realizing the method.
Data transfer between a main memory and an input/output device, via a conventional input/output channel apparatus, is performed in units of data bus widths. Memory interleaving is utilized in the main memory, to improve its performance. The length of data to be interleaved is a plurality of times the data bus width.
For some time, there has been strong demand for an increase in the speed data transfer through the input/output apparatus. When write accessing is performed, a memory write request, a write address, and write data are transferred to the main memory, and transfer delay with respect to the input/output channel apparatus does not occur. So as to increase the data transfer speed during read access, for reading out data from the main memory to the input/output device, a memory read request may be output to the main memory, and then the next memory read request may be output before the read data in response to the first memory read request is sent to the input/output device. However, as is shown in U.S. Pat. No. 4,598,362, a memory control unit in the main memory processes a request for a not-busy memory bank first. Therefore, there is no assurance that the input/output channel apparatus will receive read-out data in the same order as that of requests due to the dependency of the read out operation on the busy status of the respective memory banks. For this reason, a data string may be output in a disordered fashion. In order to solve this problem, tag information may be added to a memory read request, and the read-out data ordered in accordance with the tag information. However, such a control scheme is complex, resulting in inconvenience.
If the length of the transfer data matches with the boundaries between the memory banks of the main memory, the arrangement of the input/output channel apparatus can be simplified slightly. However, the size of the data bus area occupying the back plane is then undesirably increased. In order to realize a compact product, the data bus width in the system bus must be minimized. However, if the data length, i.e., the data bus width, is excessively decreased, the control process required for transferring data of a length defined by boundaries of the memory banks becomes more complicated, thereby decreasing the data transfer speed.